`timescale  1 ns/1 ps

module axi4_bram_tb();

`ifdef SIMULATE
`include "../../axi_sim/axi4_bfm.svh"
`include "../../axi_sim/axi4_drive.svh"

axi4_bfm  axi4_bfm_i();

axi4_drive  axi4_drive_h;

initial
begin
    axi4_drive_h = new(axi4_bfm_i);
    @(posedge  axi4_bfm_i.s_aresetn);
    axi4_drive_h.init();
    axi4_drive_h.write_config();
    axi4_drive_h.read_config();
    //#1us axi4_drive_h.write_burst(4, 4);
    #1us axi4_drive_h.write_dword('h00, 32'h11223344);
    #1us axi4_drive_h.write_dword('h04, 32'h22000000);
    #1us axi4_drive_h.write_dword('h08, 32'h33000000);
    #1us axi4_drive_h.write_dword('h0c, 32'haa000000);
    //#1us axi4_drive_h.read_dword(32'h00000004);
    #1us axi4_drive_h.read_burst(32'h00000000, 4);
    //#1us axi4_drive_h.write_dword('h04, 32'h00000011);
    //#1us axi4_drive_h.write_dword('h04, 32'h00000022);
    //#1us axi4_drive_h.read_dword(32'h00000000);

    //forever
    //begin
        //wait(interrupt == 1)
        //axi4_drive_h.read_dword(32'h00000000);
    //end
end

axi4_full_bram axi4_full_bramEx01
(
    .rsta_busy       (  rsta_busy           ),
    .rstb_busy       (  rstb_busy           ),
    .s_aclk          (  axi4_bfm_i.s_aclk              ),
    .s_aresetn       (  axi4_bfm_i.s_aresetn           ),
    .s_axi_awid      (  axi4_bfm_i.s_axi_awid          ),
    .s_axi_awaddr    (  axi4_bfm_i.s_axi_awaddr        ),
    .s_axi_awlen     (  axi4_bfm_i.s_axi_awlen         ),
    .s_axi_awsize    (  axi4_bfm_i.s_axi_awsize        ),
    .s_axi_awburst   (  axi4_bfm_i.s_axi_awburst       ),
    .s_axi_awvalid   (  axi4_bfm_i.s_axi_awvalid       ),
    .s_axi_awready   (  axi4_bfm_i.s_axi_awready       ),
    .s_axi_wdata     (  axi4_bfm_i.s_axi_wdata         ),
    .s_axi_wstrb     (  axi4_bfm_i.s_axi_wstrb         ),
    .s_axi_wlast     (  axi4_bfm_i.s_axi_wlast         ),
    .s_axi_wvalid    (  axi4_bfm_i.s_axi_wvalid        ),
    .s_axi_wready    (  axi4_bfm_i.s_axi_wready        ),
    .s_axi_bid       (  axi4_bfm_i.s_axi_bid           ),
    .s_axi_bresp     (  axi4_bfm_i.s_axi_bresp         ),
    .s_axi_bvalid    (  axi4_bfm_i.s_axi_bvalid        ),
    .s_axi_bready    (  axi4_bfm_i.s_axi_bready        ),
    .s_axi_arid      (  axi4_bfm_i.s_axi_arid          ),
    .s_axi_araddr    (  axi4_bfm_i.s_axi_araddr        ),
    .s_axi_arlen     (  axi4_bfm_i.s_axi_arlen         ),
    .s_axi_arsize    (  axi4_bfm_i.s_axi_arsize        ),
    .s_axi_arburst   (  axi4_bfm_i.s_axi_arburst       ),
    .s_axi_arvalid   (  axi4_bfm_i.s_axi_arvalid       ),
    .s_axi_arready   (  axi4_bfm_i.s_axi_arready       ),
    .s_axi_rid       (  axi4_bfm_i.s_axi_rid           ),
    .s_axi_rdata     (  axi4_bfm_i.s_axi_rdata         ),
    .s_axi_rresp     (  axi4_bfm_i.s_axi_rresp         ),
    .s_axi_rlast     (  axi4_bfm_i.s_axi_rlast         ),
    .s_axi_rvalid    (  axi4_bfm_i.s_axi_rvalid        ),
    .s_axi_rready    (  axi4_bfm_i.s_axi_rready        )
);
`else
reg                     clk = 0;
always
    #(1s/100_000_000/2) clk = ~clk;

reg     axi_write_enable = 0;
reg                     rst = 0;
initial
begin
    #1us; rst = 1;
    #1us; rst = 0;

    #1us; axi_write_enable = 1;
    #1us; axi_write_enable = 0;
end


    wire   [03:00]                     m_axi_awid;         // x
    wire   [31:00]                     m_axi_awaddr;
    wire   [07:00]                     m_axi_awlen;        // x
    wire   [02:00]                     m_axi_awsize;       // x
    wire   [01:00]                     m_axi_awburst;      // x
    wire                               m_axi_awvalid;
    wire                               m_axi_awready;
    wire   [01:00]                     m_axi_awlock;       // x
    wire   [03:00]                     m_axi_awcache;      // x
    wire   [02:00]                     m_axi_awprot;       // x

    wire   [03:00]                     m_axi_wid;          // x
    wire   [31:00]                     m_axi_wdata;
    wire   [03:00]                     m_axi_wstrb;
    wire                               m_axi_wlast;        // x
    wire                               m_axi_wvalid;
    wire                               m_axi_wready;
    
    wire   [03:00]                     m_axi_bid;          // x
    wire   [01:00]                     m_axi_bresp;
    wire                               m_axi_bvalid;
    wire                               m_axi_bready;

    wire   [03:00]                     m_axi_arid;         // x
    wire   [31:00]                     m_axi_araddr;
    wire   [07:00]                     m_axi_arlen;        // x
    wire   [02:00]                     m_axi_arsize;       // x
    wire   [01:00]                     m_axi_arburst;      // x
    wire                               m_axi_arvalid;
    wire                               m_axi_arready;
    wire   [01:00]                     m_axi_arlock;       // x
    wire   [03:00]                     m_axi_arcache;      // x
    wire   [02:00]                     m_axi_arprot;       // x

    wire   [03:00]                     m_axi_rid;          // x
    wire   [31:00]                     m_axi_rdata;
    wire   [01:00]                     m_axi_rresp;
    wire                               m_axi_rlast;        // x
    wire                               m_axi_rvalid;
    wire                               m_axi_rready;


axi_master #
(
    .C_M_TARGET_SLAVE_BASE_ADDR  (  32'h00000000                ),
    .C_M_AXI_BURST_LEN           (  1                           ),
    .C_M_AXI_ID_WIDTH            (  4                           ),
    .C_M_AXI_ADDR_WIDTH          (  32                          ),
    .C_M_AXI_DATA_WIDTH          (  32                          )
)
axi_masterEx01
(
    .m_axi_clk                   (  clk                             ),
    .m_axi_aresetn               (  ~rst                            ),
    .axi_write_enable            (  axi_write_enable                ),
    .m_axi_awid                  (  m_axi_awid                      ),
    .m_axi_awaddr                (  m_axi_awaddr                    ),
    .m_axi_awlen                 (  m_axi_awlen                     ),
    .m_axi_awsize                (  m_axi_awsize                    ),
    .m_axi_awburst               (  m_axi_awburst                   ),
    .m_axi_awvalid               (  m_axi_awvalid                   ),
    .m_axi_awready               (  m_axi_awready                   ),
    .m_axi_awlock                (  m_axi_awlock                    ),
    .m_axi_awcache               (  m_axi_awcache                   ),
    .m_axi_awprot                (  m_axi_awprot                    ),
    .m_axi_wid                   (  m_axi_wid                       ),
    .m_axi_wdata                 (  m_axi_wdata                     ),
    .m_axi_wstrb                 (  m_axi_wstrb                     ),
    .m_axi_wlast                 (  m_axi_wlast                     ),
    .m_axi_wvalid                (  m_axi_wvalid                    ),
    .m_axi_wready                (  m_axi_wready                    ),
    .m_axi_bid                   (  m_axi_bid                       ),
    .m_axi_bresp                 (  m_axi_bresp                     ),
    .m_axi_bvalid                (  m_axi_bvalid                    ),
    .m_axi_bready                (  m_axi_bready                    ),
    .m_axi_arid                  (  m_axi_arid                      ),
    .m_axi_araddr                (  m_axi_araddr                    ),
    .m_axi_arlen                 (  m_axi_arlen                     ),
    .m_axi_arsize                (  m_axi_arsize                    ),
    .m_axi_arburst               (  m_axi_arburst                   ),
    .m_axi_arvalid               (  m_axi_arvalid                   ),
    .m_axi_arready               (  m_axi_arready                   ),
    .m_axi_arlock                (  m_axi_arlock                    ),
    .m_axi_arcache               (  m_axi_arcache                   ),
    .m_axi_arprot                (  m_axi_arprot                    ),
    .m_axi_rid                   (  m_axi_rid                       ),
    .m_axi_rdata                 (  m_axi_rdata                     ),
    .m_axi_rresp                 (  m_axi_rresp                     ),
    .m_axi_rlast                 (  m_axi_rlast                     ),
    .m_axi_rvalid                (  m_axi_rvalid                    ),
    .m_axi_rready                (  m_axi_rready                    )
);

axi4_full_bram axi4_full_bramEx01
(
    .rsta_busy       (  rsta_busy           ),
    .rstb_busy       (  rstb_busy           ),
    .s_aclk          (  clk              ),
    .s_aresetn       (  ~rst           ),
    .s_axi_awid      (  m_axi_awid          ),
    .s_axi_awaddr    (  m_axi_awaddr        ),
    .s_axi_awlen     (  m_axi_awlen         ),
    .s_axi_awsize    (  m_axi_awsize        ),
    .s_axi_awburst   (  m_axi_awburst       ),
    .s_axi_awvalid   (  m_axi_awvalid       ),
    .s_axi_awready   (  m_axi_awready       ),
    .s_axi_wdata     (  m_axi_wdata         ),
    .s_axi_wstrb     (  m_axi_wstrb         ),
    .s_axi_wlast     (  m_axi_wlast         ),
    .s_axi_wvalid    (  m_axi_wvalid        ),
    .s_axi_wready    (  m_axi_wready        ),
    .s_axi_bid       (  m_axi_bid           ),
    .s_axi_bresp     (  m_axi_bresp         ),
    .s_axi_bvalid    (  m_axi_bvalid        ),
    .s_axi_bready    (  m_axi_bready        ),
    .s_axi_arid      (  m_axi_arid          ),
    .s_axi_araddr    (  m_axi_araddr        ),
    .s_axi_arlen     (  m_axi_arlen         ),
    .s_axi_arsize    (  m_axi_arsize        ),
    .s_axi_arburst   (  m_axi_arburst       ),
    .s_axi_arvalid   (  m_axi_arvalid       ),
    .s_axi_arready   (  m_axi_arready       ),
    .s_axi_rid       (  m_axi_rid           ),
    .s_axi_rdata     (  m_axi_rdata         ),
    .s_axi_rresp     (  m_axi_rresp         ),
    .s_axi_rlast     (  m_axi_rlast         ),
    .s_axi_rvalid    (  m_axi_rvalid        ),
    .s_axi_rready    (  m_axi_rready        )
);
`endif
endmodule
